ADDER X-SC Manual do Utilizador descarregar pdf (Página 65)

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 65

begin

-- Wallace tree

-- first level

ha1 : ha

port map(a => p01, b => p10,

vdd => vdd, vss => vss,

sum => p1, carry => h1c);

fa1 : fa

port map(a => p02, b => p11, cin => p20,

vdd => vdd, vss => vss,

sum => f1s, cout => f1c);

fa2 : fa

port map(a => p03, b => p12, cin => p21,

vdd => vdd, vss => vss,

sum => f2s, cout => f2c);

fa3 : fa

port map(a => p13, b => p22, cin => p31,

vdd => vdd, vss => vss,

sum => f3s, cout => f3c);

ha2 : ha

port map(a => p23, b => p32,

vdd => vdd, vss => vss,

sum => h2s, carry => h2c);

-- second level

ha3 : ha

port map(a => f1s, b => h1c,

vdd => vdd, vss => vss,

sum => p2, carry => p3b);

fa4 : fa

port map(a => f2s, b => f1c, cin => p30,

vdd => vdd, vss => vss,

sum => p3a, cout => p4b);

ha4 : ha

port map(a => f3s, b => f2c,

vdd => vdd, vss => vss,

sum => p4a, carry => p5b);

ha5 : ha

port map(a => h2s, b => f3c,

vdd => vdd, vss => vss,

sum => p5a, carry => p6b);

ha6 : ha

port map(a => p33, b => h2c,

vdd => vdd, vss => vss,

sum => p6a, carry => p7b);

end structural;

Since we already synthesized its basic blocks we can describe the tree as above. For the synthesis process we

have several choices. We will apply here FlatBeh to obtain a behavioral description of the adder tree.

% flatbeh mywallace mywallace

Then we will apply to it BOOM, BOOG and LOON (of course, we can also process it with only BOOG and

LOON).

% boom -l 3 -d 0 mywallace wallace

% boog wallace swallace -x 0 -m 4

% loon -x 0 -m 4 swallace wallace

1 2 ... 60 61 62 63 64 65 66 67 68 69 70 ... 86 87

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ADDER X-SC Manual do Utilizador Página 65

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