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1.1. ASIMUT 17

Table 1.1: Options in ASIMUT.

Option Description

-b

The RTL circuit description is a behavioral one

-backdelay [min, max, typ] delayﬁle Use delayﬁle (.ext) ﬁle of backannotated delays.

-bdd

Use BDDs (Binary Decision Diagram) to represent expressions.

-c

Run only the compilation stage.

-core coreﬁle

At error dump the state of the circuit in both an ascii (.c or) ﬁle

and a binary (.sav) ﬁle.

-d/jointfilesconvert/358990/bg[sbpldc] Call the debugger (developer use only).

-defaultdelay (-dd) Use only null delays (no after clause in the VHDL ﬁle).

-ﬁxeddelay value (-fd value) Fix all the delays in the description to value.

-h

Display the ASIMUT help ﬁle.

-i value

Initialize all signals of the description to value. This can be 0 or 1.

-i saveﬁle

Read a .sav saveﬁle and use it to initialize the description.

-inspect instancename

Produce a pattern ﬁle for the interface of the instance identiﬁed by

instancename.

-l n

Print at most n characters for pattern labels. Default n is 15.

-nores

Do not generate the output pattern ﬁle

-p n

Load at most n patterns from the input pattern ﬁle each time. A

value of 0 (default) for n loads the whole input pattern ﬁle.

-t

Trace signals when making BDDs (developer use).

-transport

Use transport delay mo del (default is inertial).

-zerodelay (-zd) Make all the delays of the VHDL description null delays.

This output tells us that the maximum allowed number of errors is 10. And, that the suﬃx (extension) of the

behavioral, pattern and delay ﬁles are .vbe, .pat and .dly, respectively. We must be careful when using any

option (check the available ones with asimut -h). For example, the −bdd option makes the simulation faster but

would increase memory requirements. We must be careful also when naming ﬁles. If we intend to use the −i

option, the initialization ﬁle must not be named 1 or 0 or it will be considered as the initialization value. On

the otherhand, options like −p let us reduce memory allocation when a great number of patterns is simulated

(after every n patterns, the simulation result is printed in the output pattern ﬁle).

Not all the VHDL syntax is supported in Alliance. We can use only a subset of VHDL to describe our

designs. So, descriptions out of the supported subset also cause errors in ASIMUT at compilation time. We

review brieﬂy in the following sections the VHDL subset supported by the Alliance tools.

1.1.1 VHDL Subset Supported in Alliance

The Alliance VHDL subset is IEEE Std 1076-1987 compliant. This makes the descriptions written in this subset

usable with any commercial/free VHDL tool. The Alliance subset let us describe only digital synchronous

circuits. A circuit described with this subset is a design entity that can be a submodule of other entities or

the top level module of a design. Each design entity in VHDL has a deﬁnition of the ports that let the design

communicate with the outside world. The ports could be of type in, out, and inout. The in type ports handle

input of values to the circuit. The out type the output values of the circuit. If both input and output is allowed

through a p ort it must declared of type inout.

The predeﬁned set of types handled by the ports is shown in Table 1.2. Remember that user deﬁned types

are not supported in the VHDL subset used in Alliance. In VHDL we can specify an entity both structurally

and behaviorally in one ﬁle. In other words we can mix descriptions in one des ign ﬁle. However in the subset

supported by Alliance this is not allowed. We must use one .vbe ﬁle for the behavioral description of the entity

and a .vst ﬁle for its structural description. In a hierarchical design only the leaf entities are required to have a

corresponding behavioral description. In the following subsections we brieﬂy describe the details of the syntax

supported in the structural and behavioral subsets used in Alliance.

1.1.1.1 Structural V HDL Subset

In the subset supported in Alliance the structural description of a design can include signal declarations and

component declarations. The internal signals can be any of the types of Table 1.2. The structural description

itself is a set of component instantations. Component ports must be declared with the same name, type and kind

and in the same order in which they appear in the corresponding entity declaration. Component interconnection

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