ADDER X-SC Manual do Utilizador descarregar pdf (Página 63)

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 63

With this we have a synthesized structural description of our original partial product generator. For the other

two blocks we need as basic (leaf) block half and full adder circuits. The design and synthesis of them is shown

in the following section.

2.1.2 Half and Full Adder design

In the design of the adder tree and output adder of the multiplier we will use the half adder and full adder

of Figure 2.4 and Figure 2.5, respectively. The half adder is given by the following behavioral description

(remember that we must provide both the behavioral and structural description of our leaf designs).

-- half adder

entity ha is

port(a,b,vdd,vss : in bit;

sum,carry : out bit);

end ha;

--behavior

architecture vbe of ha is

signal a_bar, b_bar : bit;

begin

a_bar <= NOT a;

b_bar <= NOT b;

sum <= (a_bar AND b) OR (a AND b_bar);

carry <= a AND b;

end vbe;

As could you notice this does not correspond to the circuit of Figure 2.4. We will obtain that description using

BOOM optimizing for delay.

% boom -l 3 -d 0 myha ha

We obtain the following behavioral ﬁle that is indeed the ﬂow description of the circuit of Figure 2.4.

-- VHDL data flow description generated from ‘ha‘

-- date : Mon Feb 14 11:05:26 2005

-- Entity Declaration

ENTITY ha IS

PORT (

a : in BIT; -- a

b : in BIT; -- b

vdd : in BIT; -- vdd

vss : in BIT; -- vss

sum : out BIT; -- sum

carry : out BIT -- carry

);

END ha;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF ha IS

BEGIN

carry <= (b AND a);

sum <= (b XOR a);

END;

We also run BOOG and LOON on this circuit as follows.

% boog ha myha -x 0 -m 4

% loon -x 0 -m 4 myha ha

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