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1.8. FLATBEH 37
As could be notice from the output, no errors has been detected. And the layout generated by OCP and NERO
does not contain violations to the design rules spe cified in the cmos .rds file.
The options available in DRUC are shown in Table 1.9. The option -h generates many intermediate files,
but there is no documentation about its use.
Table 1.9: Options Available for the DRUC Tool.
Option Description
-v
Verbose mode on. Each step of the DRC is output on the standard output
-h
Hierarchical design rule checking. Generates lots of files locally, to be used by future
invocations of druc.
1.8 FlatBeh
The FlatTBeh (Flattens to Behavioral) tool generates a behavioral description from a structural one. It
could be used to check if the description obtained in the synthesis process of a design is correct. It flattens
the structural description of the target design down to its leaf behavioral components. Then, it uses those
descriptions to create a behavioral description of the target design. This tool can be started with the following
command.
flatbeh root_structural_file [ output_file ]
This tool has no options. Its parameters are only the root structural design and the ouput file name. We must
check that MBK CATA LIB is set to the path where the descriptions of the design are given. MBK IN LO
must be set to vst. Also, if needed, we can set MBK CATAL NAME to the file (normally CATAL) that lists the
files names of the behavioral description where FlatBeh must stop the flattening of the structural ro ot design.
Let’ apply it to our mux oo.vst design generated by BOOG.
% flatbeh mux_oo mux_oo
@@@@@@@@@ @@@@ @@@@@@@ @@@
@@ @ @@ @ @@ @@ @@
@@ @ @@ @@ @@ @@ @@
@@ @@ @@@@ @@ @@ @@ @@@@@ @@ @@@
@@ @ @@ @@ @ @@@@@@@@ @@ @@ @ @ @@@ @@
@@@@@@ @@ @@ @@ @@ @@@@@@ @@ @@ @ @ @@
@@ @ @@ @@@@@ @@ @@ @@ @@@@@@@@@ @@ @@
@@ @@ @@ @@ @@ @@ @@ @@ @@ @@
@@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@
@@ @@ @@ @@@ @@ @ @@ @@ @@ @@ @@ @@
@@@@@@ @@@@@@ @@@@ @@ @@@@ @@@@@@@@ @@@@ @@@@ @@@@
a netlist abstractor
Alliance CAD System 5.0 20040928, flatbeh 5.0 [2000/11/01]
Copyright (c) 1993-2005, ASIM/LIP6/UPMC
Author(s): Fran?ois DONNET, Huu Nghia VUONG
========================= Environnement =========================
MBK_WORK_LIB = .
MBK_CATA_LIB = .:/usr/local/alliance/cells/sxlib:/usr/local/alliance/cells/dp_s xlib
:/usr/local/alliance/cells/rflib:/usr/local/alliance/cells/romlib:/usr/local/alliance/cells/ramlib
:/usr/local/alliance/cells/padlib
MBK_CATAL_NAME = CATAL
============================== Files === ==== ==== ==== ==== === ==== ====
Netlist file = mux_oo.vst
Output file = mux_oo.vbe
===================================================================
Loading ’./mux_oo.vst’
flattening figure mux_oo
loading inv_x2
loading ao2o22_x2
Restoring array’s orders
BEH : Saving ’mux_oo’ in a vhdl file (vbe)
- Contents 3
- 4 CONTENTS 4
- List of Figures 5
- 6 LIST OF FIGURES 6
- List of Tables 7
- 8 LIST OF TABLES 8
- 10 LIST OF TABLES 10
- Chapter 1 11
- 1.1. ASIMUT 15 15
- 1.1. ASIMUT 19 19
- 1.3 BOOG 26
- 1.4 BOOM 26
- 1.5 COUGAR 29
- 1.5. COUGAR 31 31
- 1.5. COUGAR 33 33
- 1.6 DREAL 34
- 1.7 DRUC 36
- 1.8 FlatBeh 37
- 1.9 FLATLO 39
- 1.10 FLATPH 39
- 1.11 FMI 39
- 1.12 FSP 41
- 1.13 GENPAT 41
- 1.14 GRAAL 43
- 1.15 K2F 43
- 1.16 L2P 44
- Figure 1.18 46
- 1.17 LOON 47
- 1.18 LVX 48
- 1.19 MOKA 48
- 1.20 NERO 49
- 1.21 OCP 50
- 1.22 Proof 51
- 1.23 Ring 53
- 1.24 S2R 53
- 1.25 SCAPIN 53
- 1.26 SYF 54
- 1.27 VASY 55
- 1.28 X2Y 55
- 1.29 XFSM 56
- 1.30 XPAT 56
- 1.31 XSCH 57
- 1.32 XVPN 57
- Combinational Design Examples 59
- (a) (b) (c) 60
- 2.1.3 Adder Tree 64
- 2.1.4 Output Adder 66
- 2.1.5 4-bit Multiplier 67
- And set a few new ones 83
- Bibliography 87
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