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28 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLS
output file to visualize all the delay paths of it. Running BOOG will give the following output.
% boog mux_o mux_oo -x 1 -m 2
@@@@@@@ @@@@ @
@@ @@ @@ @@
@@ @@ @@ @
@@ @@ @@@ @@@ @@
@@ @@ @@ @@ @@ @@ @@
@@@@@@ @@ @@ @@ @@ @@ @@@@@
@@ @@ @@ @@ @@ @@ @@ @ @@
@@ @@ @@ @@ @@ @@ @@ @ @@
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Binding and Optimizing On Gates
Alliance CAD System 5.0 20040928, boog 5.0 [2003/01/09]
Copyright (c) 2000-2005, ASIM/LIP6/UPMC
Author(s): Fran?ois Donnet
E-mail : [email protected]
MBK_VDD : vdd
MBK_VSS : vss
MBK_IN_LO : vst
MBK_OUT_LO : vst
MBK_WORK_LIB : .
MBK_TARGET_LIB : /usr/local/alliance/cell s/s xlib
Reading default parameter...
50% area - 50% delay optimization
Reading file ’mux_o.vbe’...
Controlling file ’mux_o.vbe’...
Reading lib ’/usr/local/alliance/cells/s xlib ’...
Mapping Warning: Cell ’halfadder_x4’ isn’t supported
Mapping Warning: Cell ’halfadder_x2’ isn’t supported
Mapping Warning: Cell ’fulladder_x4’ isn’t supported
Mapping Warning: Cell ’fulladder_x2’ isn’t supported
Controlling lib ’/usr/local/alliance/cel ls/s xlib ’...
Preparing file ’mux_o.vbe’...
Capacitances on file ’mux_o.vbe’...
Unflattening file ’mux_o.vbe’...
Mapping file ’mux_o.vbe’...
Saving file ’mux_oo.vst’...
Quick estimated critical path (no warranty)...657 ps from ’c’ to ’q’
Quick estimated area (with over-cell routing)...3000 lambda?
Details...
ao2o22_x2: 1
inv_x2: 1
Total: 2
Saving delay gradient in xsch color file ’mux_oo.xsc’...
End of boog...
The synthesis process with BOOM and BOOG is shown in Figure 1.9. To see the schematics of the mux design
Figure 1.9: The synthesis process using BOOM and BOOG
we use the graphical tool XSCH. We call it with the following command.
% xsch
Then from its File menu we can choose any .vst file in our working directory. Let’s see first our original
mux.vst structural design. This is shown in Figure 1.10. Let’s see now the optimized and synthesized mux
circuit (mux oo.vst). This is shown in Figure 1.11. As could be seen from these figures the original mux circuit
is formed by discrete components while the optimized and mapped design is made of only two cells, one inverter
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