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Modify the stim.vec file to include your actual test vectors. Check that the ripple carry
adder still works (at a sufficiently slow cycle time) to verify that your vectors are correct.
The repeated simulations to find the cycle time get tedious. In the project directory, you
can find a short Perl script called cycletime.pl that repeatedly runs the design at different
cycle times, looking for errors. It reports the minimum cycle time and the EDP. Invoke
it by running
./cycletime.pl
Now, netlist your improved adder design. Find its EDP. Tune your schematic and try to
improve the results. Manual simulations again are tedious, so you may find that using
SPICE’s SWEEP capabilities or enhancing cycletime.pl to automatically tune other
variables is preferable.
Deliverables
There are two deliverables and a design review in this project.
Milestone A: Schematics
Turn in a legible schematic of your 10-bit adder. If you use any cells that are not part of
muddlib, turn in schematics for those cells as well.
The testvectors provided are woefully inadequate to convince a skeptical engineer that
the RTL is correct. Write a testplan outlining a more comprehensive set of vectors
sufficient to demonstrate that the adder is likely to work, and turn in your new adder.tv
along with the testplan.
Report whether the transistor-level netlist simulates in the addertest testbench for your
new set of vectors with no errors.
Milestone B: Adder Optimization
Try to make your adder have the best possible energy × delay product. You are free to
modify your schematics if you wish to improve a design; if so, turn in the modified
designs.
Turn in SPICE simulations demonstrating the maximum operating frequency of your
design, the energy at that frequency, and the energy × delay product. Use the SPICE
testbench. Be careful that you choose your frequency conservatively enough that the
adder will work correctly on any set of test vectors. You may wish to add test vectors to
boost your confidence.
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