ADDER A.I.M. Manual do Utilizador

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 1Experiment No 1 Realization of Boolean Expression using L

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 10Experiment No.3 Parallel adder Aim: (i) Realization of

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 11Truth Table for adder: Inputs Outputs Decimal No Car

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 12Truth table for Excess-3 to BCD conversion: Excess – 3 i

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 13Experiment No: 4 Code Conversion Aim: To realizes a co

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 14Logic Diagram for Binary to Gray code conversion: G0 G

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 15Simplification for Gray Code: B2 B1 B0

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 16Experiments No. 5 Multiplexer / Demultiplexer Aim : i)

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 174:1 MUX using NAND Gates Truth Table Inputs Select li

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 18Pin Diagram of IC 74153( Dual 4 : 1 Mux)

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 192:4 Decoder using NAND Gate: Truth Table: Select Line

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 2Logic Diagram: Using Basic gate. Using NAND gate.

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 20Decoder / Demultiplexer: IC 74139 E1 Ena

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 21For Sum: For Carry: Full adder u

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 22For Carry: Half Subtractor using

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 23 Full Subtractor using IC 74153 Truth T

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 24 3-bit Binary to Gray conversion using IC

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 253-bit Binary to Gray conversion using IC74139: Truth Tabl

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 26Experiment No 6 Magnitude Comparator. Aim:- a) To real

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 27b) Two bit Comparator: Design: A>B A=B

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 280 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 29Truth table for 4-bit Comparator: Input Data Inputs (Fr

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 3Using NOR gate. Truth Table: A B C Y 0 0 0 0 0

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 30Experiment No 7 Decoder / Encoder Aim: a) Use of deco

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 31Study of Priority Encoder Decimal to BCD conversion usin

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 32Octal to Binary conversion using IC 74148:

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 33Experiment No: 8 Flip-Flops Aim : a) Realization of (i

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 34Procedure: 1. Connection are made as shown in Logic dia

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 35Logic Diagram of T Flip Flop: Truth table for T Flip Flo

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 36Experiments : 9 Asynchronous up / Down Counter using IC

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 37Logic Diagram for 3-bit Asynchronous up counter:

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 38Logic Diagram: 3-bit Asynchronous Down Counter:

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 39Mod N Counters: Logic Diagram for Mod 5up counter:

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 4Experiment No 2 Realization of Half/Full adder and Half/F

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 40Logic Diagram for Mod 4 Down Counter:

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 41Procedure: 1. Connections are made as shown in the Logi

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 42Experiment No – 10 3 Bit Synchronous Counter using IC 74

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 43Transition Table : Present State Next State FF-2 FF-1

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 44Wave Forms: Procedure: 1. Connections are made as sh

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 45Experiment No – 11 Counters using counter IC’s Decade C

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 46 Logic Diagram for Decade counter 7490:

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 47 State Table: Decade Counter: State Table: Mod 8 Coun

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 48 Programmable 4-bit Synchronous UP / Down decade counter.

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 49 Logic diagram for Preset value = 8, N = 6, (To count fro

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 5Half adder using NAND gate: Design For Half subtractor: T

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 50 Preset Value = 8, N = 6, (To count from 8 to 3) Down – 7

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 51 Function Table: Load Clear Clk-up Clk-down Mo

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 52 Truth Table: From 3 to 8 from 12 to 5 Cloc

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 53 Procedure: 1. Connections are made as shown in

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 54 Experiment No – 12 Shift Register Aim: To

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 55 DS: Serial input data (to be shifted) D3, D2, D1

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 56 Truth Table: Clock Serial Q0 Q1 Q2 Q3

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 57 Truth Table: Clock Parallel Data Inputs

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 58 Truth Table: Mode M Clock Ds Parallel data input Se

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 59 Truth Table: Clock Serial Data I/P Q0 Q1 Q2 Q3 1

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 6Half subtractor using NAND gates: Design for Full add

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 600 2 0 1 0 0 0 3 0 0 1 0 0 4 0 0 0 1 0 5

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 611. Connection are made as shown in the Logic diagram. 2.

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 62The given sequence length S = 15, ∴N = 4 Note: There is

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 63 Procedure: The give Sequence: 1000 1001 1010

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 64 a b c d e f g Vcc = 3 a = 1 b= 13 c

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 7Logic Diagram: Full adder using basic gates: Full adder

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 8Realization for Borrow Realization for Difference BCi

III Sem E&C Engg. LOGIC DESIGN LAB (10ESL38) Dept. of E&C K.I.T - Tiptur 9Procedure: 1. The IC is fixed on the IC trainer and